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Dyson came out with its first travel hair dryer, the Supersonic Travel. At 0.7lbs, this hair dryer features the same heat control as the standard Supersonic and universal voltage for travel. Check it out now

Visual Preset #03# High Voltage High-end cinematic 3D realism fused with hyper-energized electrical phenomena. Every movement generates branching plasma arcs, snapping lightning filaments, electromagnetic distortion, ionized air ripples and cascading sparks that dance across surfaces instead of conventional energy effects. Electric currents crawl over characters, weapons and environments with rhythmic pulse patterns, while shockwaves illuminate drifting particles, vapor and debris in synchronized flashes. Aggressive camera movement, dramatic perspective, volumetric light shafts, dynamic exposure shifts and dense atmospheric haze amplify every discharge, creating a world where electricity constantly reshapes the surrounding space. Feature-film rendering, physically believable materials and realistic electrical interactions preserve scale, weight and cinematic realism. Seedance 2.0 Prompt for this video: @[character re] lowers into a sprint as brilliant blue-white electricity condenses around one outstretched hand, crackling with violent intensity. Every accelerating step tears glowing fractures through puddles, while branching lightning lashes across the ground and nearby structures. The air warps with electromagnetic distortion as the fighter bursts forward in a blinding dash, piercing through the opponent's guard with a single lightning-charged palm strike. The impact erupts into an explosive sphere of plasma arcs and cascading sparks, briefly freezing the battlefield in white-blue light before the electrical current dissipates into the storm-filled sky. ...rest is visual preset.

Today on The A24 Podcast, 45 minutes of nonstop, high-voltage entertainment with The Invite's Seth Rogen and Olivia Wilde, featuring (but not limited to) their worst audition stories from movies like 8 Mile, Gravity, The Tree of Life and more. Full video now on YouTube.

2028 后限制 AI 算力硬件的不再是晶体管，而是封装！是怎么把多颗 die 封进一个 240mm 巨块并喂进 4kW 的电，然后再把热和光导给出去⚡️配图来自日本 3DIC Research Lab 「先进封装技术研讨会」我转译成了中文，中间那块剖面图，是一个超大尺寸的 3D 异构集成封装，当然这个路线图略显激进😜 - Co-Package Optics（FAU / EIC / PIC, 2λ/4λ）：光直接进封装，铜互连到头 → 这是 CPO 从"会发生"被画成 2028 默认路线的又一独立信源； - >4kW Cooling, Direct-to-Chip → Direct-to-Silicon, 直接液冷：单封装功耗破 4 千瓦，液冷从"贴芯片"进化到"贴硅"； - Vertical Power Delivery, High-voltage DC, PMIC / IVR / DTC：供电从机柜压进封装内部，垂直供电 + 高压直流 + 就近稳压 → 电已经压到封装级，催生封装内供电器件； - D2D / UCIe / micro-bump 3D / Cu direct 3D：chiplet 标准化互连、铜直连 3D 堆叠； - >10 reticle Interposer（Panel-level）/ 240×240mm² Substrate：中介层超 10 个光罩、改用面板级工艺，超大多层基板 → 封装设备/材料（日韩台供应链），基板成新瓶颈； 这么大封装最易翘曲，良率/可靠性是隐性门槛。但传统基板已撑不住 >200×200mm² 的 mega-size 封装，需要全新 building block！

New information about @Tesla's Cybercab has been revealed in public EPA documents. • Front-wheel drive • Battery capacity: ~48 kWh • 219 horsepower • Curb weight: 3,113 lbs • GVWR: 3,730 lbs • Motor power: 163kW • Voltage: 326v Equivalent All Electric Range is listed at 418 miles, with 375 miles of highway range, but the final EPA range rating is usually a decent bit lower. Tesla has previously stated the Cybercab has about 300 miles of range. Filing:

🚨 BMW HAS SOLVED ONE OF HYDROGEN’S BIGGEST PACKAGING PROBLEMS. The company has developed a new “Hydrogen Flat Storage” system for the iX5 that uses seven slim hydrogen tanks instead of two large ones. This flat design fits into the same space as the high-voltage battery pack used in the electric iX5. This is significant because it allows BMW to build the hydrogen-powered iX5 on the same production line as petrol, diesel, plug-in hybrid, and fully electric versions without major changes to the factory or vehicle architecture. The system stores 7kg of hydrogen at 700 bar and gives the iX5 an estimated range of 385 miles. BMW plans to start series production of the iX5 Hydrogen in 2028, using a fuel cell developed in partnership with Toyota. Why this matters: • One of the biggest barriers to hydrogen vehicles has been packaging the tanks without sacrificing interior space or requiring completely separate production lines • This modular “flat storage” approach makes hydrogen powertrains much more practical to manufacture at scale • It gives BMW flexibility to produce multiple powertrains on one platform depending on demand and regional infrastructure The deeper implication: While battery electric vehicles currently dominate, BMW is continuing to develop hydrogen as a parallel technology, particularly for larger vehicles and longer-range applications. Being able to build both BEVs and FCEVs on the same line is a pragmatic engineering step that could make hydrogen vehicles more commercially viable in the future if the refuelling infrastructure catches up. Follow for more frontier automotive and energy technology.

🚨 DIAMOND IS ABOUT TO REPLACE SILICON IN NEXT-GEN CHIPS. Scientists are now producing large single-crystal CVD diamond wafers that could revolutionize electronics. Diamond conducts heat 5× better than copper and over 10× better than silicon while also handling extreme voltages, high frequencies, and radiation. Why this matters: • Thermal Superpower: Diamond acts as its own heat sink, solving one of the biggest problems in high-power chips • Ultra Wide Bandgap: Handles massive voltage and extreme temperatures without breaking down • High Frequencies: Electrons move incredibly fast, perfect for 6G, radar, and advanced telecom • Radiation Hardness: Ideal for satellites, space tech, and nuclear applications The deeper implication is massive: We’re at the early stages of a materials revolution. As silicon hits its physical limits with heat and power, diamond one of the most extraordinary materials in nature could power the next era of AI chips, electric vehicles, and aerospace systems. What do you think will diamond semiconductors become mainstream in the 2030s? Follow for more frontier materials science and future technology.

Intel’s EMIB Packaging Is Growing Rapidly — Silicon Capacitors Are Taking Off Too Silicon capacitors are poised for explosive growth in the AI semiconductor space. Intel has been found to be planning a large-scale adoption of silicon capacitors starting next year, in order to enhance the performance of its in-house 2.5D packaging technology, “EMIB.” The most clearly visible source of demand is Google. Google plans to launch its next-generation AI accelerator, “v8e,” in the second half of next year, and has adopted an EMIB substrate with embedded silicon capacitors for that chip. With other Big Tech companies such as Amazon also currently applying EMIB, analysts say demand could increase sharply. According to industry sources on the 27th, Intel plans to apply silicon capacitors to its 2.5D packaging starting next year. Intel Adopts “Silicon Capacitors” for 2.5D Packaging… Google AI Chip Gets First Application 2.5D is an advanced packaging technology that inserts a thin-film interposer between the semiconductor and the substrate. Because it can connect circuits at higher density compared with conventional packaging that uses only a substrate, demand is rising in the AI and HPC fields. To improve cost efficiency in 2.5D packaging, Intel devised its own technology called EMIB. Rather than using a broad, spread-out interposer, EMIB connects chip to chip using a small silicon bridge. Since bridges only need to be placed where chip-to-chip connections are required, chips can be arranged more flexibly and efficiently. Recently, EMIB has been drawing attention as an alternative to TSMC, which had been leading the existing 2.5D packaging market. This is because TSMC’s 2.5D packaging capacity is suffering from a supply shortage amid the rapid development of the AI industry. Indeed, global Big Tech player Google is also paying attention to EMIB. Google has decided to adopt EMIB for its in-house AI semiconductor “v8e,” which it plans to launch in the second half of next year. Under this structure, TSMC handles chip mass production, MediaTek handles design and manufacturing support, and Intel handles packaging. However, there have been concerns that EMIB is gradually showing limitations in providing stable power supply for AI semiconductors, which consume large amounts of power. Accordingly, Intel plans to introduce new technologies such as silicon capacitors and through-silicon vias (TSV) to ensure stable packaging for the v8e. A capacitor is a component that stores and releases electricity in an electronic circuit. In the case of silicon capacitors, their resistance (ESL/ESR) is more than 100 times lower than that of conventional multilayer ceramic capacitors (MLCC), minimizing the signal loss that occurs in high-performance semiconductors. They can also be designed in an ultra-thin structure based on a silicon wafer, enabling high-density integration. A semiconductor industry official explained, “Because the voltage drop (the phenomenon of voltage decreasing) that occurs in the high-frequency region within AI chips is difficult to solve with MLCC, we understand that Intel is adopting silicon capacitors as a solution,” adding, “The relevant supply chain is now in place, and mass production is set to begin in earnest next year.” EMIB-T Is Already on a Growth Trajectory — The Related Ecosystem and Market Are Expanding Together Intel has also inserted TSVs, which serve as power-delivery channels, into the silicon bridge. The key point is that by using TSVs to shorten the power-delivery path between the substrate and the chip, Intel has improved power efficiency and signal integrity. Intel calls this “EMIB-T.” The industry expects the EMIB-T and silicon capacitor markets to grow rapidly. This is because Japan’s Ibiden — one of the major companies that mass-produces semiconductor substrates for EMIB-T — is aggressively pursuing capital investment. Previously, Ibiden had planned to build its Kawashima (Gama) plant in Gifu Prefecture as a substrate plant for Intel CPUs. However, it postponed that schedule and decided in the first half of this year to officially convert the Gama plant into a mass-production line for EMIB-T substrates. The investment is 220 billion yen (about KRW 2.1 trillion). In its recent earnings announcement, Ibiden stated, “Operation of the Gama plant will begin in 2027 and enter full-scale mass production in 2028,” adding, “EMIB-T substrate capacity is currently far short of demand. However, adding further capacity is quite difficult, so we are discussing options with our customers.” A semiconductor industry official explained, “Ibiden’s EMIB-T-dedicated line is being built with most of the investment coming from customers such as Google, Amazon, and Intel,” adding, “This demonstrates that AI semiconductors based on EMIB-T will grow significantly going forward, and silicon capacitors are likely to expand alongside them.”

华为τ scaling定律营销策略，无非是more than moore的广义摩尔定律的另一种说法而已 作为芯片架构师，我更感兴趣的，还是芯片密度提升，ppt上41%能耗提升和12.7%性能提升，到底是怎么实现的 看完了论文，感觉华为这次创新，本质上是用设计复杂度高 + 高制造成本 + 超前散热，一定程度弥补了工艺差距 ----------------- 1. 华为芯片堆叠带来的等效密度提升，是虚假宣传还是真的，是不是工艺突破？有没有实打实的好处？ 等效密度提升的来源，是两片芯片用hybrid bonding技术绑在一起，投影面积理论上能减小一半，但第一代不是全芯片双层折叠，而是选择性折叠关键logic，所以只有大概53%的芯片面积实现了折叠(密度155->238)，等到后面几代折叠面积会逐渐增大，到2030年接近全折叠（密度155->292） 这2026第一代等效密度从 2025 年 155 MTr/mm² 跳到 2026 年 238 MTr/mm²，时钟频率也提升了12.7%，功耗比提升41%，表面上看似乎和工艺突破没有什么区别，但有一点重要区别就是leakage power华为从头到尾没有提，只要工艺节点不变，gate leakage、junction leakage 不会因为 3D stacking 自动改善 2030年到2031年的等效密度突变，大概率是来自于2层堆叠到3层堆叠，正如2025到2026年的等效密度突变，时钟频率突变，来自单层到2层折叠 所以从leakage没提这个事来看，这个2031年等效1.4nm，和工艺节点上的突破没有联系。 本质上是用设计复杂度高 + 高成本 + 超前散热 + 超前部署advanced packaging，一定程度弥补了工艺差距 ----------- 那么这样看起来虚假的等效密度提升，有用处吗？好处在哪里？ 有的，设计上topology折叠，原来要跑几毫米的水平走线，折叠后变成了几十微米。降低了super buffer/bus的长度，降低了clock tree的深度（clock depth -42%、clock wire -28%），clock skew也带来了改良(-25%)，这对动态功耗的改善是实实在在的。部分critical path的缩短，也让时钟频率的上升更容易 所以ppt roadmap上performance的提升，从2025年到2026年上升了12.7%，大部分都是来自于时钟频率的上升（12.7%） 所以好处基本上是topology拆分电路逻辑设计上带来的提升 既然没有实质上的工艺提升，华为芯片堆叠带来等效密度提升的trade off代价在哪里？ 三个代价：散热超前发展，设计复杂度高，制造成本变高 最大的代价就是热密度的同步上升，理论上logic on logic都是CPU execution发热最严重的区域，这部分折叠起来相当于功耗密度直接翻倍，但算上41% power efficiency改善，功耗密度仍只比非堆叠方案高40%左右。所以第一代只能对最关键的部分做折叠，大概只占全芯片面积的53%。 所以散热技术也被逼的超前发展，直接上毫米级的MEMS风扇，做micro-cooling fan。 另外的代价就是设计复杂度的变高，critical path的折叠，哪个部分的logic能折叠，折叠之后又会带来从前端到后端的巨大变化要推翻重来 现有的所有EDA工具也不可能支持3D topology，论文自己也承认，full-scale LogicFolding需要全新的3D-native EDA toolchain，把多层stacked dies当作单一连续设计实体处理。哪些logic能折叠、折叠后的inter-die timing closure怎么做，Physical Design（PD）也是难点 制造成本也会更高，被迫超前部署advanced packaging封装，1.5~2um的hybrid bonding + logic on logic都是很有挑战需要显著更高的成本 以前一层wafer做一次光刻；现在两层wafer分别做光刻再bonding，加上hybrid bonding的overlay控制（论文要求<0.5μm）、TSV、KOZ keep-out zone、冗余修复、良率乘法损失，每颗芯片的制造成本和测试成本都要显著上升 -------------------------- 2. Tau scaling这个说法，scaling的到底是什么，这个scaling技术路线是不是一次性的design topology红利？潜力如何？持续进步的空间在哪里？ τ Scaling的核心主张是：用时间常数τ替代几何线宽作为全栈优化目标，在器件、电路、芯片、系统四个层级分别压缩特征延迟 公式本身没有任何新物理。"关注瓶颈延迟"是所有架构师都在做的事情。整个行业都知道互联RC是延迟瓶颈，TSMC每一代工艺都在用low-k dielectrics/semi-damascene等手段降RC。把一个众所周知的优化方向包装成"定律"是显然的营销宣传手段，本质是More than Moore的广义摩尔定律的另一种说法 抛开marketing，华为目前所谓RC delay的改善，本质上是芯片堆叠之后，topology距离缩短，让匹配的effective RC都变小，不是RC工艺常数 至于scaling的意思，是能持续发展的一条roadmap。这里的持续改善路径指的是，全芯片堆叠的层数越来越多，从25~30年的2层堆叠，到31年开始的3层堆叠，以后甚至会考虑4层堆叠 第一代折叠技术甚至不是全芯片双层折叠，而是选择性折叠关键logic，所以只有大概53%的芯片面积实现了折叠(密度155->238)，等到后面几代折叠面积会逐渐增大，到2030年接近全折叠（密度155->292）。2031年的roadmap之所以会出现一个阶跃，就是因为那是从2层折叠到3层折叠的时间点。 但需要注意的是，这个scaling方法的边际效应是逐渐缩小的，折叠成双层的收益是100%，2->3层的收益就只有50%，如果2035年再从3->4层堆叠，收益就只有33%了 另外随着堆叠层数变高，上面说到的三个挑战，散热，设计复杂度，成本，都是越来越大 --------------------- 3. 华为的芯片堆叠，是不是TSMC/AMD已经有的hybrid bonding技术？华为做到的是cache on logic，cache on cache，还是logic on logic，logic on logic最大的散热问题是怎么解决的？ 是已经有的技术没错，但同时也是把现有技术指标做到了领先也是真的，3D堆叠本身不是新技术，TSMC的hybrid bonding量产还是6um，华为论文给出Kirin 2026的hybrid bonding pitch是1.5μm 我在刚刚看到华为的堆叠消息之后，第一反应也是怀疑和AMD的3D V cache类似，它主要把 SRAM cache 叠在 已经有的L3 cache 区域上，通常会避免直接堆在最热的 CPU execution logic 上，就是避免散热问题，毕竟SRAM 的功耗密度和热点特性与high-activity logic 不一样，如果最热的logic on logic堆叠，散热恐怕会碰到困难 但看了更多数据之后，clock buffer -56%、clock depth -42%、clock wire -28%，这些只有在core内部的clock distribution被重构时才可能发生。纯SRAM stacking不会碰core内部的clock tree。另外如果只是cache on cache，大概率是不需要单独MEMS微型风扇额外散热的，证据普遍都指向logic on logic方式 华为这个技术的精妙之处在于，logic on logic 折叠之后热密度并没有翻倍，而是因为topology的好处，能耗下降了30%，这样热密度只上升了40~50% 而第一代没有完全把整个最热的execution logic 100%堆叠起来，论文也明确说selectively applied along key critical paths，只是大概53%有选择性关键路径会堆叠起来，可能颗粒度都没有那么好，只是IP堆叠在IP上，那么热密度上升也许能维持在20%以内 但这条道路继续前行，超前发展的散热就成了必然，现在是MEMS微型毫米级的主动散热风扇，紧贴处理器传导效率高，和华为手机一样，散热堆料特别足，而且技术领先同行。 以后怕是要把HBM7/8的微流道散热技术提前用起来了，毕竟HBM7/8要上24+层堆叠，华为很可能要在提前用上下个世代的散热技术了 ------------------------- 4. 从架构角度来说，最重要的问题，华为41%的power efficiency（能耗比）提升，到底是怎么实现的？为什么AMD的3D V cache没有这么大的提升？ 首先确定41%的定义。论文只说"SoC performance-core power efficiency improved by 41%"，没有给出benchmark名称、Voltage/Freq点、温度条件、功耗边界。但PPT roadmap上有一个关键线索：ISO-Power Performance的数字，2025年是2.75，2026年是3.1，提升12.7% 这个时钟频率提升12.7%完全一致，可以理解为，同功耗的性能提升是12.7%，绝大部分是时钟频率提升带来的 至于能耗比上优化的猜测是，LogicFolding缩短critical path → 在固定Vdd下Fmax从2.75GHz提升到3.1GHz → 这意味着在原来的2.75GHz频率下，有了约12.7%的timing headroom → 这个空间在iso-performance模式下可以换成更低的Vdd 另外的能耗比的提升，可能也来自于电路折叠之后，cache hit latency的下降。从业界经验来看，一般L2/L3 cache hit latency下降10%，CPU整体性能会有至少5%的提升 ppt里显示SRAM latency下降30%，估计会有一部分转化为cache hit latency的下降 AMD的3D V cache没有这么大的提升，主要是因为AMD的底层logic die并没有重新设计，3D cache的延迟latency不仅没有减小反而加大，只是增加了cache大小，收益不如latency下降那么明显。 另一方面，clock skew的下降,critical路径变短，造成电路timing变好，意味着华为可以使用更低的vdd（猜测甚至能低7~8%），以及路径缩短所带来的RC的下降(考虑到clock buffer -56%、wire -28%、SRAM pJ/bit -24%这些数字，比如C_eff下降10~15%合理)，再加上clock tree的整体缩短和下降，确实是有可能在部分Voltage/Freq点做到同性能下，做到30%的功耗下降的，而30%的功耗下降换算过来就是41%的power efficiency 对比苹果和高通，每一代手机芯片在iso-power下单核性能一般提升10-20%，iso-performance下功耗一般降30-40%，这是V/F曲线的特性决定的，所以从经验上来说，数字是对的上的。 所以这个power efficiency（能耗比）的提升，从现有的数字上来说可以从topology推导出来是合理的，可能真的和工艺节点没有太大关系 ---------------------------- 5. 这个技术路线有没有可复制性，其他家会不会效仿？ 短期内不会大规模效仿，因为性价比和风险收益比来说不好。长期来看，这个方向所有人都在走，只是名字不一样 华为做LogicFolding的根本驱动力是制裁，工艺节点被卡在7nm，只能在封装，散热，和设计层面想办法弥补。华为也为此付出了不小的代价：散热成本，设计复杂度，以及制造成本更高（包括良率）。这是一个被逼出来的路线，不是一个自然选择 其他玩家在用TSMC就能做到正常的经济迭代，是没有必要冒着这个风险，去超前迭代散热技术和设计复杂度的 长期来看，Intel的Foveros、TSMC的SoIC、AMD的MI300的3D stacking都在朝同一个方向走。如果继续追最先进节点的经济性持续恶化，那么"固定一个成熟节点+3D topology optimization"的路线会越来越有吸引力 散热方面，MEMS微型风扇和微流道也会成为未来HBM散热的主流 ------------------- 总结一下，华为这次的创新，绝对是值得尊重的，在制裁环境下，用极高的设计复杂度和成本，在一个被锁定的工艺节点上大胆重新设计，榨出了一次大的topology红利，虽然它有天花板。每多加一层的边际收益递减（堆叠1->2层, 2->3层, 3->4层，提升百分比变小），leakage无法解决，散热越来越难，3D EDA工具链更是全新的挑战。 但这个Tau scaling不是一条可以走十年的指数增长路径，每次爬完一个台阶，下一个台阶更难爬，而且台阶更矮收益更小，华为以后想缩小差距，还得再想想靠什么其他的路线