Bleys Goodson (@bleysg) “It is a 2 to 4T param model. They are serving it across 70-100 wafers. To get he” — TopicDigg

It is a 2 to 4T param model. They are serving it across 70-100 wafers. To get healthy serving characteristics, they are essentially putting at most one layer per wafer, and the model is in the ballpark of 70-90 layers. There's a couple of different ways this could be served and model sizes implied by that. One is if they keep the heavy KV caches they've used before. Another is if they go with lighter KV cache designs more akin to DeepSeekV4 or Hybrid SSM models. The fact that they've partnered with Cerebras and designed with the hardware in mind means they're much more likely to have gone the second route. That SRAM bandwidth is too precious for a heavy KV cache. As such, something like the below is the center of probability mass: 3T total, 150B active, 70 layers.